This invention relates to an analog to digital converter and in particular to a flash type analog to digital converter having low electric power consumption.
For some prior art flash type analog to digital converters, 2.sup.N comparators are required, N being the number of bits representing the resolution. For this reason, as the number of bits increases, the number of necessary comparators increases significantly, which gives rise to an increase in the electric power consumption and an increase in the chip size, when the comparators are made of ICs.
In order to solve this problem, there is known a method by which the effective number of bits is increased by superposing a predetermined number of off-sets on the reference voltage of the analog to digital converter and adding outputs of the analog to digital conversion for every different off-set over a predetermined period. In this specification a converter according to this method is called a cyclic averaging analog to digital converter. Techniques relating to this cyclic type averaging analog to digital converter are described in JP-A-57-129526 and JP-A-62-88434.
In these prior art examples, in order to superpose a predetermined number of off-sets on the reference voltage, a method is adopted, as shown in FIG. 10, by which resistors 112 and 113 are connected with the two extremities of a series of resistors 101 supplying different reference voltages to a plurality of comparators 102 driven in parallel, and the resistances of those resistors 112 and 113 are varied. As an example, this can be accomplished by utilizing a plurality of resistors which are controlled by means of switches. In FIG. 10, reference numeral 103 indicates an encoder which transforms outputs of the group of comparators 102 into binary codes; 3 indicates an adder; V.sub.S1 and V.sub.S2 are source voltages, respectively, given from the exterior; V.sub.IN is an input analog voltage; and 31 is a digital output.
The prior art technique described above is effective in that it is possible to increase the number of bits of the flash type analog to digital converter, i.e. the resolution thereof, while keeping the increase in the scale of the circuit and the electric power consumption to a low level. However, in practice there is a problem in implementing the circuit by an IC circuit. For example, consider a case where the reference voltage given to the group of comparators is shifted by 4 steps so that the number of bits of the analog to digital converter is increased by 2. In this case the amount of shift of the reference voltage is equal to 1/4 of the voltage corresponding to 1 LSB of the original flash type analog to digital converter. Consequently, the resistance of each of the resistors 101 connected in series being r, the variable amount .DELTA.R in the resistance of the resistors 112 and 113 should be equal to r/4. Further, since the variation in the resistance, which is as small as r/4 is provided by turning on and off the switches inserted in series with respect to the resistors, it is not possible to obtain an exact reference voltage, unless the ON resistance of the switch is taken into account. In particular, it is difficult to provide it by using a switch disposed within an IC.
In addition, the prior art technique described above can be applied only to flash type analog to digital converters having linear conversion characteristics.